Timing of data output

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This topic contains 5 replies, has 2 voices, and was last updated by  Faisal 1 year, 10 months ago.

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    I have modified my detector board data output for the OpenPET v2.0 by looking at your dataout and processdata components. There is one thing that is not obvious as the way the code is written I can not determine the clock edges relationship of the signals valid_i, slice_i and data_i. I am assuming it is as follows.

    clh_i __|++i_|++i_|++i_|++i_|++I_|++I_|++I_|++I_|++

    adc_clk_i __|++++i____|++++i____|++++i____|++++i____|++++

    data_i __|+++++++++|+++++++++|+++++++++|+++++++++i_____

    slice_i __|+++++++++++++++++++i___________________|++++++
    valid_i __|++++++++|+++++++++|+++++++++|++++++++++i_____

    Is this correct.`




    Hello Roger,

    Are you asking about a specific component in the firmware or the final output from DB to IO?

    If you are asking about dataout.vhd

    clk_i is not really used. Everything is being output on both edges of adcs_clk.

    Altera recommends using altddio_out to align output signals and clocks, and that’s what we are doing.

    valid_i and data_i are aligned in mode_osc.vhd on the rising edge of adcs_clk.

    slice_i is not really used in dataout.vhd, however, DB’s slice_out pin is connected to valid_o, therefore, it is used as a valid_i in IO.

    Finally, as you know we use DDR on the data pins. Note that you need to take a look at the SDC file in order to get the timing right.

    I suggest that you copy/paste the SDC rules used for DDR as they will take you a long time to reproduce.



    I missed this

    	s_slice_i(0) <= valid_i;
    		slice_o      <= s_slice_o(0);
    		slice_out_synced : altddio_out

    I am using the altera ddr_out the same as your dataout

    Thanks Roger

    • This reply was modified 1 year, 10 months ago by  Faisal.



    Don’t forget to take a look at db16ch.sdc

    especially these two sections:

    # db fpga to io fpga source sync timing


    # ddr false path statements to simplify timing analysis


    I have looked a the sdc file. It looks like you delay the data and valid/slice_o more then the clock which is what I would except.
    You calculate the delay in the sdc file which use some line that I am not familiar with. Can you give me the min max delays for the output. I use the sdc file to see if I come up with the same values.



    The code is in tcl. you can get the values either by calculating them or from timequest. Here you go:

    max -0.100
    min -11.900
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